`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:14:16 04/01/2014 
// Design Name: 
// Module Name:    DEMO 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DEMO(signal,rst,resume_button,clk,HS, VS, red, green, blue);
input [3:0] signal;
input rst,resume_button, clk;
	 
output HS;
output VS;
output [2:0] red;
output [2:0] green;
output [1:0] blue;

wire [7:0] R0,R1,R2,R3,R4,R5,R6,R7;
wire [11:0]pc;
wire [15:0] selection;
wire CPU_clk;
//wire [6:0] signal;

//choose
assign selection = (signal == 0) ? {8'd0,R0}:
						 (signal == 1) ? {8'd0,R1}:
						 (signal == 2) ? {8'd0,R2}:
						 (signal == 3) ? {8'd0,R3}:
						 (signal == 4) ? {8'd0,R4}:
						 (signal == 5) ? {8'd0,R5}:
						 (signal == 6) ? {8'd0,R6}:
						 (signal == 7) ? {8'd0,R7}:
						  {4'd0,pc};
						 
//clk
CLK_div25MHz M3(CPU_clk, clk);	


//TOP Module
TOP T1(R0,R1,R2,R3,R4,R5,R6,R7,pc,cmp_flag,vid_line,aud_line,poll_line,CPU_clk,rst,resume_button);


//VGA
TOP_VGA VGA (HS,VS,red,green,blue,clk,selection);
endmodule
